Latency hiding on COMA multiprocessors

Latency Hiding on COMA

Cache-only memory access (COMA) multiprocessors support scalable coherent shared memory with a uniform memory access programming model. The local portion of shared memory associated with a processor is organized as a cache. This cache-based organization of memory results in long remote memory access latencies. Latency-hiding mechanisms can reduce eeective remote memory access latency by making ...

Low Latency Messages on Distributed Memory Multiprocessors

This paper describes many of the issues in developing an efficient interface for comnaunication on distributed memory machines and proposes a portable interface. Although the hardware component of message latency is less than one microsecond on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 microseconds. The reas...

Communication Latency Hiding

Latency-Hiding Work Stealing

With the rise of multicore computers, parallel applications no longer consist solely of computational, batch workloads, but also include applications that may, for example, take input from a user, access secondary storage or the network, or perform remote procedure calls. Such operations can incur substantial latency, requiring the program to wait for a response. In the current state of the art...

Unallocated Memory Space in COMA Multiprocessors

Cache only memory architecture (COMA) for distributed shared memory multiprocessors attempts to provide high utilization of local memory by organizing the local memory as a large cache, called attraction memory (AM), without traditional main memory. To facilitate caching of replicated data, it is desirable to have some of the physical storage space in the AMs left unallocated, i.e. not utilized...